This invention relates to the field of digital data acquisition and logic analysis, and more particularly to the field of counting and timing intervals with enhanced resolution in a logic analyzer or other digital data acquisition instrument.
Logic analyzers are digital data acquisition instruments that allow a user to acquire and analyze digital data from a large number of logic signals, such as the address, data, and control lines of a microprocessor. The logic analyzer periodically compares each of these logic signals to a reference threshold in order to determine which logic state, high or low, each of the lines is in.
Trigger sections allow operators to specify when in time they would like to acquire data, i.e. which data they are interested in. This is necessary because even the largest acquisition memories are quickly filled by all the data occurring in a fast electronic system. The trigger is the most important reference time in a logic analyzer, since it initiates the sequence of activities associated with data acquisition and is frequently the reference time for other measurements.
Using the human interface of the trigger section, the operator specifies a sequence of events or particular conditions, which, if they occur, indicate that this is the data that the operator is interested in. While the logic analyzer is running waiting for the specified trigger conditions to occur, the digital data from the system under test is sent to a circular memory, which may be overwritten and refilled many times before the trigger occurs indicating that the interval of interest has been reached.
When the triggering conditions have been satisfied, the flow of new data into the circular memory is interrupted and the data present is saved. This storage of digital data can occur immediately upon the occurrence of the trigger condition or after a variable delay. If the writing to memory is stopped immediately, the memory contains data reflecting the activity that occurred prior to the trigger event, i.e. "pretrigger" data. Conversely, if the memory is allowed to keep filling for its whole length after the trigger condition occurs, the contents of the memory reflects entirely the activity that occurred immediately after the trigger event, i.e., is "posttrigger" data. Typically, any one of a number of combinations of pretrigger and posttrigger data storage can be selected. Which combination a user chooses is dictated by the problem they are trying to solve and which conditions in the temporal vicinity of the problem can be identified well enough to program the trigger machine.
The trigger sections of some logic analyzers also contain one or more counter/timers. These allow the trigger condition to be specified in terms of a number of occurrences of some event or in terms of a time. For example, a timer can be used to measure the interval between two events and the trigger section can be programmed to produce a trigger when this time exceeds a certain value. Or, the counter/timer can be made to count every occurrence of event A and to reset upon the occurrence of event B, with the trigger section programmed to produce a trigger if the count of A occurrences reaches a particular value.
A logic analyzer has an internal clock rate that places a limit on how fast it can process incoming digital data and how much resolution it can have. Resolution is the minimum time interval that it can distinguish. Normally, if a logic analyzer has a 5ns internal clock period, it can not make any measurement with more resolution than 5ns. However, it is possible to acquire data with more resolution than it has previously been possible to perform counter/timer operations on it. By using both edges of one clock signal, or by using two clock signals 180 degrees out of phase, an internal clock signal with a 5ns clock period can be used to acquire data every 2.5ns. But, as this data moves into the logic analyzer, two of these 2.5ns samples must be processed with every 5ns clock signal. Previously, counter/timer measurements have been limited in their resolution to the period of the acquisition system clock.
What is desired is to have a logic analyzer, or other digital data acquisition instrument, with a counter/timer that can reconstruct the higher resolution with which data was originally acquired using multiple phases of the logic analyzer system clock, rather than having the resolution be limited to the period of the acquisition system clock.